1. Field of Invention
The present invention pertains generally to automatic test techniques for semiconductor state machines or logic devices, the outputs of which are a function of their previous state as well as their inputs, and more specifically to a process for automatically generating tests by an algebraic recursion technique which is suitable for any device capable of being described by Boolean state equations.
2. Description of the Background
There are two primary approaches to automatic test generation (ATG) for sequential networks. First, the topological technique which works at the gate level of a logic network and involves schematic traversal of the internal architecture of the device in order to sensitize an output to a fault. Secondly, the algebraic technique is independent of a particular architectural implementation the device functionality is concerned only with external pin faults. The topological process has previously been used to generate tests for combinatorial logic devices but there has been no general solution for sequential devices, as the problem of initialization (setting the internal registers of a logic device to a known state) has been viewed as intractable, due to the large number of possible previous states of a device. An automated algebraic test process to identify static pin faults for sequential logic devices, in circuit, would greatly speed test development and be valuable for implementing designs which are testable.